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Color LCD video display technology


DC component of the signal on the base to land in the capacitor, the output voltage to move the equivalent of zero-average DC component of the range. As a result of the different DC component video signal, so the video signal through the coupling capacitor, a synchronization header height difference. (2) If the video signal is mixed with some low-frequency AC interference signal,[link widoczny dla zalogowanych], will cause the sync level changes. (3) video transmission system frequency decline in the low frequency, low frequency distortion of the signal will also cause the sync level changes. Missing sync pulse height, making the distortion after the sampled data. To solve this problem, can clamp circuit. Clamp circuit usually free, for positive polarity video signal, the signal at the bottom of the clamp. After clamping the video signal, the input video amplifier with adjustable magnification, so as to achieve image display LCD contrast control. Another use of the video amplifier is to convert the video signal level to the ADC full scale voltage range of the device. 5.4 conversion mode shake the video signal conversion module to do during the show, stop in the blanking period. ADC analog and digital circuit components should be separate power supply,[link widoczny dla zalogowanych], to prevent the transient interference generated by digital circuit coupled to the analog circuits, affecting sampling accuracy. Input power supply bypass capacitors should be installed near, high and low frequency noise suppression. Taking particular account of the proper wiring and grounding techniques to achieve optimal device ADC operation. 5.5 storage memory to store one frame of digital information, for a resolution of 512 to 512 of the liquid crystal display, such as the sampling efficiency of 6 bits, the frame memory capacity of 512 ~ 512 ~ 6. In order to reduce the requirements on memory access and to control the speed of simple detection can be the memory of two programs to do the transformed data model in the frame under the control of strobe pulse, a write,[link widoczny dla zalogowanych], while another frame is read out. Two memory options shown in Figure 3. Figure 3 color LCD video display technology Xiong Zhiyong 2l view of the video signal uses interlaced scanning, the address generator is set to step 2, Yu-odd field identification signal through, so that complete a frame memory storing digital video data. Video module 6 Universal design to consider since the 90's, the EDA companies have launched a number of non-programming tool for the design of input, it] allows designers to use their most convenient and familiar design (block diagram, state diagram, the true value tables and text) conceptual design. Then the simulation analysis, the designer modified design model based on the analysis and re-simulation, and finally consolidated by the EDA tools to automatically generate the required VHDL (or HDL). EDA tools through the simulation, the early changes in engineering design, making the whole design efficiency doubled. Therefore, the use of EDA tools, for improving the design of circuit performance, shorten the design cycle is of great practical significance. Video module's address and timing control circuit can occur ASIC implementation, can be FPGA or EPLD. Known address in the design and timing control circuit occurs. The number of devices to use some of the most. Small standard components, they often take up most of the board-area, through Asia designed to solve the above problem. Meanwhile, the hardware programming, improve design flexibility. Universal video display module from the considerations,[link widoczny dla zalogowanych], the video display module should be able to wasp display different video signal format. At the same time can wasp support different display aspect ratio. In order to achieve universal video display module can be used for the following two aspects: (1) the use of different characteristics of video signal formats, automatic identification of video types, which video module automatically adjusts the sampling clock frequency, display a different standard video signals to meet the requirements of . For example, the system can display PAL and NTSC video module, in between two vertical sync signal pulse on the line count. If the line number is 262 pulses. The field frequency is 60Hz the NTSC system video signal. If the line number is 312 pulses,[link widoczny dla zalogowanych], the spot frequency of 5OHz the PAL system video signals. (2) According to the resolution characteristics of the LCD indicators. Software control to change the sampling clock frequency can be achieved by supporting different aspect ratio display purposes.
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